Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a semiconductor memory device that increases the efficiency of a column redundancy circuit for repairing a defective unit cell and reducing a total area in a semiconductor memory device.
In a system with a variety of semiconductor devices, a semiconductor memory device may serve as data storage. The semiconductor memory device may output data corresponding to address received from a data processor, for example, a central processing unit (CPU), or store data received from the data processor into memory cells selected by address.
As the operating speed of the system increases and semiconductor integrated circuit technologies advance, higher speed input/output operations of semiconductor memory devices are desired. There is an ongoing demand for semiconductor memory devices that can store more data, read and write data rapidly, and reduce power consumption. In meeting such demands, widths of signal lines for transferring various signals in a semiconductor memory device, and the size of a unit cell for storing data have been becoming gradually smaller. As a result, a number of signal lines and a number of unit cells included in a semiconductor chip are increasing in order to meet the demands for high capacity semiconductor memory devices.
However, the design and fabrication process of a high capacity semiconductor memory device is also becoming more difficult. For example, as elements included in a semiconductor memory device shrink in size, defects tend to occur. Particularly, defects may exist between signal lines or between a signal line and a unit cell, where such defects contribute to an increase in the defect rate of semiconductor memory devices. When such defects are not properly repaired/compensated in semiconductor memory devices, production yields may suffer. As a way to address such a concern, semiconductor memory devices may include a column redundancy circuit configured to detect and repair defects.
A column redundancy circuit, which may be used to replace defective unit cells, is often included in each of a plurality of banks in a semiconductor memory device. Each bank may include cell matrices having unit cells, a row control region where circuits for accessing row addresses are provided, and a column control region where circuits for accessing column addresses are provided. The column redundancy circuit may include a row redundancy circuit configured to repair a row address of a defective unit cell, and a column redundancy circuit configured to repair a column address of the defective unit cell. The row redundancy circuit and the column redundancy circuit are respectively included in the row control region and the column control region in each bank.
FIG. 1 shows a diagram illustrating a conventional semiconductor memory device having a stack bank structure.
Referring to FIG. 1, column control regions of adjacent banks are arranged to contact each other in the conventional semiconductor memory device of the stack bank structure.
The semiconductor memory device in FIG. 1 includes a plurality of banks. Each of the banks typically includes cell matrices including a plurality of unit cells, a row control region including a row decoder (XDEC, which is not shown) configured to control word lines, and a column control region including a column decoder (YDEC) configured to control column lines. The column control region includes the column decoder (YDEC) configured to decode data output from the unit cells and the column redundancy circuit. In addition, the column control region of each bank in the semiconductor memory device includes a column redundancy circuit implemented with a plurality of fuses.
Each of adjacent banks includes a corresponding column redundancy circuit. A column redundancy circuit receives a column address for controlling the cell matrix in the bank, and functions to replace a column address corresponding to a defective unit cell with a column address of a spare cell for repairing the defective unit cell when a defect occurs in the unit cell. Such an operation is referred to as “a repairing operation”.
Accordingly, as illustrated in FIG. 1, the semiconductor memory device includes a column redundancy circuit corresponding to column address of an upper bank BANK0, and a column redundancy circuit corresponding to column address of a lower bank BANK1.
FIG. 2 is a block diagram illustrating a conventional column redundancy circuit of the upper bank BANK0 in FIG. 1.
A conventional semiconductor may include a column redundancy circuit corresponding to column address of a first bank BANK0 and a column redundancy circuit corresponding to column address of a second bank BANK1, respectively. A fuse set 222 included in the first bank BANK0 detects a defective unit cell of the first bank BANK0 only.
Referring to FIG. 2, the column redundancy circuit of the first bank BANK0 includes a fuse unit 220 and a comparison unit 240.
The fuse unit 220 includes the fuse set 222 and a defective cell address generation unit 226.
The fuse set 222 outputs a defect indication signal YA_B0 based on reset signal WLCB_B0 and cell matrix signals XMAT_B0<0:n>. The reset signal WLCB_B0 is activated to reset a repair detect signal REP_DET at node A shown in FIG. 3 when the first bank BANK0 enters a precharge mode. The cell matrix signals XMAT_B0<0:n> are selectively activated to indicate a cell matrix selected among the cell matrices in the bank. The defect indication signal YA_B0 is activated to indicate that there is a defective unit cell in the selected cell matrix.
The defective cell address generation unit 226 receives the cell matrix signals XMAT_B0<0:n> and a bank enable signal WLCPB_LAT_B0. The bank enable signal WLCPB_LAT_B0 is activated when the first bank BANK0 is enabled. The defective cell address generation unit 226 is configured to output the column defective cell address YRA_B0 indicating locations of the defective unit cells. The number of the defective cell address generation units 226 is equal to the number of bits of the column address of the corresponding first bank BANK0. An operation of the defective cell address generation unit 226 is apparent to a person of ordinary skill in the art and thus, a further description thereof is omitted.
The comparison unit 240 compares the column defective cell address YRA_B0 output from the defective cell address generation unit 226 with an external column address AYT when the defect indication signal YA_B0 is activated. The comparison unit 240 outputs a redundancy enable signal SYEB_0 when the external column address AYT is the same as the column defective cell address YRA_B0.
FIG. 3 is a detailed circuit diagram of the conventional fuse set 222 in FIG. 2.
Referring to FIG. 3, the fuse set 222 includes a reset unit 310, a repair detect signal generation unit 320 and a latch unit 330.
The reset unit 310 resets the repair detect signal REP_DET at the node A to a logic high level in response to the reset signal WLCB_B0.
The reset unit 310 includes a PMOS transistor which resets the repair detect signal REP_DET to a logic high level of a power supply voltage VDD when the reset signal WLCB_B0 of a logic low level is input through a gate of the PMOS transistor.
While FIG. 3 does not show, the reset signal WLCB_B0 is generated by combining an active command and a precharge command of the first bank BANK0. The active command enables a corresponding cell matrix in response to a specific column address for a read operation or write operation.
Accordingly, the reset signal WLCB_B0 enables the reset unit 310 during a precharge mode of the first bank BANK0.
The repair detect signal generation unit 320 generates the repair detect signal REP_DET and provides it to the node A in response to the cell matrix signals XMAT_B0<0:n> and a cut state of the fuse.
The cell matrix signals XMAT_B0<0:n> represent an enabled cell matrix during an active mode of the first bank BANK0 for a read/write operation.
The repair detect signal generation unit 320 includes a plurality of unit fuse sets 320_1 to 320—n, which are coupled in parallel between the node A and a ground voltage (VSS) terminal.
Hereinafter, a first unit fuse set 320_1 is described in detail as an example of the plurality of unit fuse sets 320_1 to 320—n. The first unit fuse set 320_1 includes an NMOS transistor which applies a ground voltage VSS to a fuse F_1 when a first cell matrix signal XMAT_B0<0> of a logic high level is input at a gate of the NMOS transistor. The first unit fuse set 320_1 includes the fuse F_1 which applies the ground voltage VSS from the NMOS transistor to the node A in response to a cut state of the fuse F_1. The cut state of the fuse F_1 includes a cut-off state and a no-cut state.
The latch unit 330 latches the repair detect signal REP_DET at the node A to output the latched signal as the defect indication signal YA_B0 of the first bank BANK0. The latch unit 330 may include an inverter-latch which inverts and latches a repair detect signal.
The fuse F_1 corresponding to a defective unit cell detected during testing of a semiconductor memory device is cut off among the plurality fuses coupled in parallel each other. When a corresponding one of the cell matrix signals XMAT_B0<0:n> is enabled, the NMOS transistor corresponding to a selected cell matrix is turned-on to thereby apply a logic low level signal of the ground voltage VSS. However, when the selected cell matrix includes a defective unit cell, the repair detect signal REP_DET maintains its reset state of a logic high level since the fuse is in a cut-off state. On the contrary, when the selected cell matrix does not include a defective unit cell, the repair detect signal REP_DET has a logic low level and the defect indication signal YA_B0 of a logic low level since the fuse is in a no-cut state.
FIG. 4 is a timing diagram illustrating operations of the fuse set 222 in FIG. 3. Here, the operation of the fuse set 222 is started at a reset mode in which the repair detect signal REP_DET at the node A is reset to a logic high level by the reset signal WLCB_B0 of a logic low level. The NMOS transistor included in the fuse set F_1 is not turned-on by the cell matrix signal XMAT_B0<0> of a logic low level. Therefore, since the ground voltage VSS is not supplied to the node A, the repair detect signal REP_DET at the node A substantially maintains the logic high level.
The cell matrix signal XMAT_B0<0> transitions from the logic low level to a logic high level when the reset signal WLCB_B0 becomes a logic high level.
The ground voltage VSS is supplied to the fuse F_1 when the NMOS transistor is turned-on by the cell matrix signal XMAT_B0<0> of a logic high level.
When the selected cell matrix includes the defective unit cell, the ground voltage VSS is not supplied to the node A since the fuse F_1 is cut. The repair detect signal REP_DET at the node A substantially maintains the previous logic high level. The latch unit 330 outputs the repair detect signal REP_DET of a logic high level as the defect indication signal YA_B0.
On the contrary, when the selected cell matrix does not include a defective unit cell, the ground voltage VSS is supplied to the node A since the fuse F_1 is not cut. The repair detect signal REP_DET at the node A transitions from the logic high level to a logic low level. The latch unit 330 outputs the repair detect signal REP_DET of the logic low level as the defect indication signal YA_B0.
In a semiconductor memory device, it is desirable to reduce a total area of the semiconductor memory device for improving productivity.
Referring to FIGS. 1 to 4, the conventional banks each include a separate fuse set. Thus, while the conventional fuse set 222 detects a defective cell matrix included in the corresponding bank, it does not detect a defective cell matrix included in another bank.
As a semiconductor memory device decreases in size, a greater number of semiconductor memory devices may be produced on each wafer. However, as a greater number of semiconductor memory devices may be produced on each wafer, a greater number of column redundancy circuits for replacing defective unit cells are also required. Thus, such an increase in the number of column redundancy circuits for replacing defective unit cells raises a concern in producing high integration semiconductor memory devices.